NSF/Intel Partnership on Foundational Microarchitecture Research (FoMR)

NSF/Intel Partnership on Foundational Microarchitecture Research (FoMR) Full Proposal Deadline Date: January 12, 2018 Program Guidelines: NSF 17-597   The confluence of transistor scaling, increases in the number of architecture designs per process generation, the slowing of clock frequency growth, and recent success in research exploiting Thread Level Parallelism (TLP) and Data Level Parallelism (DLP) all point to an increasing opportunity for innovative microarchitecture techniques and methodologies in delivering performance growth in the future. The NSF/Intel ... More at https://www.nsf.gov/funding/pgm_summ.jsp?pims_id=505450&WT.mc_id=USNSF_39&WT.mc_ev=click This is an NSF Upcoming Due Dates item. Follow NSF:  This email was sent using GovDelivery Communications Cloud on behalf of: National Science Foundation Update · 2415 Eisenhower Avenue, Alexandria, VA 22314 · 703-292-5111